In multiple processor computing systems there exists the need to provide memory resources so each processor can perform tasks independent of the other processor(s). There further exists a need in such systems to provide a capability for the exchange of information between the respective processors. In some processing applications, e.g., image processing, the amount of data to be transferred from the memory of a sending processor to the memory of a receiving processor can be substantial. Many configurations of communication buses, memories and processors have been developed to meet these needs in the context of varying system requirements. However, the known configurations are subject to a variety of performance restrictions, e.g., limited bus accessibility, delay penalties associated with arbitration schemes, etc.
FIG. 1A illustrates an exemplary prior art dual processor system 100 comprising a first processor 102, an associated random access memory (RAM) 104, a second processor 106 and associated RAM 108. System 100 also includes an address bus 110 and a data bus 112, the buses being coupled to data and address ports of the two processors and two RAMS. In operation, each processor gains access to the buses at different times under control of bus arbitration apparatus (not shown) in order to access its associated memory for data read or write operations. In order to transfer data between the processors, each processor has access to the memory associated with the other processor via buses 110 and 112. For example, processor 102 may gain control of the buses to read data from or write data to address locations in RAM 108.
One drawback to the configuration of system 100 is that one processor is always isolated from the bus while the other processor accesses either its associated memory or the memory associated with the other processor. Such isolation of one processor results in system operating inefficiency. Another drawback of the system 100 configuration is that each interprocessor data transfer is controlled by one of the processors and is therefore limited to the rate at which that processor can effect the transfer. As a result, a substantial amount of time would be required when a large amount of data is to be transferred from one memory into the other. A third drawback relates to the additional concerns in programming the operation of the processors to assure that in the course of data transfer operations, one processor does not mistakenly overwrite the valid data of the other processor.
A variant of the system 100 configuration is one in which RAMs 104 and 108 are actually contained in a single memory with respective memory portions dedicated to the processors and an additional common memory portion is allocated for sharing between the processors. With the memory so configured, the shared portion would be used for interprocessor data transfers. That is, data required by one processor may be written by the other processor into the common memory portion for subsequent reading by the processor requiring the data. While such a memory configuration may reduce the chance for data overwrite errors, since the common memory portion is uniquely allocated for data transfers, the configuration nevertheless generally suffers the same operating inefficiencies described above with respect to memory read/write operations in system 100.
One solution for reducing the amount of time required for data transfer in a system such as system 100 is to provide direct memory access (DMA) capability between the respective memories of the processors. In such a case, a DMA controller (not shown) would be coupled to the processors, their respective memories and to the buses in manner known in the art. Then, in accordance with memory location identifying information provided by the processor initiating the data transfer, the control of the buses would be relinquished by both processors and the data transfer would be effected by the DMA controller. As is well known, such DMA transfer is accomplished at greater speed than a processor controlled data transfer. One drawback to the use of DMA to effect the data transfer is the system inefficiency resulting from isolating both processors from the bus during the transfer. An additional drawback derives from the hardware cost associated with providing the DMA capability.
Yet another solution to the above described problems associated with effecting interprocessor data transfers is the provision of a dual ported memory for enabling data transfer between two processors. FIG. 1B illustrates a system 150 which is the same as system 100 except for the introduction of a dual ported RAM 152 shared between processors 102 and 106 and the segmentation of buses 110 and 112 to create additional address and data buses 154 and 156. Due to provision of dual ported RAM 152, each processor has no need for access to the RAM associated with the other processor and therefore has exclusive access to its associated RAM, via the data and addresses buses, for performing its own tasks. As a result, separate bus segments, illustrated in FIG. 1B as coupling dual ported RAM 152 to processors 102 and 106, can be provided for the respective processors to avoid delays that would otherwise result from bus sharing.
As is well known in the art, each processor connected to the dual ported memory has access to the entire contents of that memory. However, since both processors access the same memory, the address and data buses in the dual ported RAM must be multiplexed and the delay introduced by this logic degrades memory access performance. Further, dual ported memory operates more slowly than conventional memory, and, as a result, offers no real increase in operating speed for operations requiring the reading or writing of large amounts of data.